Semiconductor memory devices, such as non-volatile memories and the like, usually include embedded memories, such as the code memory in flash microcontrollers, which may contain proprietary programs that should not be accessible to anyone, especially one's competitors. These embedded memories require security features that allow users to program the contents of the memory, verify the contents of the memory, and then disable the memory from ever being read externally again.
Some prior art methods of protecting the contents of embedded memories include the use of lockbit features that prevent the embedded memory (hereinafter “memory”) from being read outside of a device in which it is embedded after locking. The lockbit is a type of programmable, non-volatile memory element that, when programmed or “fused,” prevents external READ operations of the memory. Since a non-volatile element is used, it can be written and then erased again, corresponding to locking and unlocking of the memory. It is desirable to have a lock/unlock capability in the memory security features in order to increase manufacturing testability and yield, and to allow reuse and reprogramming by an end-user. Currently, a common method to unlock the device would usually involve the use of a CHIPERASE command, which first erases any proprietary memory contents and then erases the lockbit fuses. In this way, the user may only reach the memory content space after the previous memory contents have been completely erased. However, it has been found that this method is prone to attack and defeat by hackers for a variety of reasons.
U.S. Pat. No. 6,229,731 to Kasai et al., U.S. Pat. No. 6,088,262 to Nasu, and U.S. Pat. No. 6,026,016 to Gufken disclose semiconductor devices having read protect circuits for protecting non-volatile memory arrays. However, in each one of these prior art semiconductor arrays, a read protection circuit is located outside of the main memory array. This does not allow the erase/unlock behavior of the lockbits, or protection circuit, to match the erase behavior of the memory array, which may allow access to the memory content space if the lockbits are unlocked before the memory contents are erased.
It is an object of the present invention to provide a semiconductor memory having a memory protection architecture and algorithm that prevents the defeat of the lockbits and guarantees that the memory contents cannot be read even when the lockbits are defeated.
It is a further object of the present invention to provide a memory protection architecture that is part of the memory array so that the erasing behavior is matched.